Pulse-echo phase discriminator using deltic processing

ABSTRACT

This disclosure is of a pulse-echo signal processor for deriving and displaying bearing angle information by measurement of the phase difference of echo signals received at two spaced points. Bearing angle determination is accomplished by processing signals received at each of the two spaced points through a moving time series DELTIC and correlating the time-compressed outputs with the transmitted signal which is correspondingly time-compressed in a stationary time series DELTIC. The correlation signals thus generated are combined to provide an unthresholded display output, in which the input signal amplitude information is preserved, and a thresholded output to a timer which indicates the desired phase difference measurement.

Wafinll Emily E li, W73:

{54] PULSE-ECE-EUI PHASE DHSCIRHMHNATER 3,646,334 2/1972 Wold 343/100 CLm ng HDEL'NQ PRWCESSHNG 3,663,956 /1972 Purcly et al. 324/83 D {75]Inventor: Lawrence F. Waiul, Llverpool, NY. Primary Emmmu Richard AFarley [73} Assignee: Genernl Electric Compnriy, Attorney carl W. Bakeret al.

Syracuse, NY.

{22] Filed: Apr. i7, W72 [57] Alldli'lR/QT C'IF' {211 A N 244392 Thisdisclosure is of a pulse-echo signal processor for deriving anddisplaying bearing angle information by measurement of the phasedifference of echo signals [52] Cl Mam/3 2 :5 ?8 received at two spacedpoints. Bearing angle determi- 51 E a Cl 3 l1 3 (Gigi 9 E; nation isaccomplished by processing signals received I at each of the two Spacedpoints through a i g time i 1 m 0 3 9 series DELTKC and correlating thetime-compressed l 8 outputs with the transmitted signal which iscorrespondingly time-compressed in a stationary time series [56}Refemmes 6mm DElL'llC. The correlation signals thus generated are UNITEDSTATES PATENTS combined to provide an unthresholded display output,

2,958,039 10/1960 Anderson 340/6 R in which the input signal amplitudeinformation is pre- 3,289,154 11/1966 Cunningham... 235/181 served, anda thresholded output to a timer which indi- 3 3/ 1968 Pryor 235/181cates the desired phase difference measurement.

3,521,044 7/1970 Costas 343/100 CL 3,591,789 7/ 1971 Hoffman et al235/181 5 (Claims, 3 Drawing Figures BEAII ESIIMER BEAMFORMER AND IIXMIT REF. IS AND PREPRocEssoR Tns PREPRocEssoR: l v l SAMPLING HARDSAMPLING CIRCUlT I |M|T CIRCUIT SAMPLING PULSE i I I i I (IKHE) i A/DA23 TRANSFER W A/D CONVERTER GATE Q coNvERTER A I I CLOCK (IMHE) l/ i ii i 38 MOVING STATIONARY MOVING TIME sERIEs TIME sERIEs TIME SERIESoELrIc DELTIc DELTIC l l/ l/ i coRRELAroR CORRELATOR 5| as v i -s9 4I- VCONVERTER CONVERTER I M I FILTER TO A-SCAN DISPLAY iemm 7% T5 73 PIZ'ML0E1". PEAK DET. -n ,I EBUMMER a- AND INTEsnaToR I INTEsnm'on SAMPLING isRuLsE TTEcTIFIIER RECTIFIER (mile) nun AND -4 Y INTEsIRaToR INTEeRRron53 V I DELAY HARD TNREsHoLoINe Rana (IOO/JSEC) LWHT cIacuIT LIMIT J siingi t m V l lq 12 3g DEL/W fie 4 a lino mam 53 DELAY moo law 5H 5mm i MIse IsEm KW TIMER smear qmgv COUPJi'lEll ;I EJEAWING rihmLE TO DlEJPLM"!PAYENTEII JLLB I I975 SHEET 1 OF 2 LEFT RIGHT BEAMFORMER XM'T BEAMEDRMERAND v AND PREPROCESSOR l5 PREPROCESSOR F |G.l

CIRCUIT LIMIT cIRCuIT SAMPLING PULSE L T (IKI-Iz) A I TRANSFER I A/DCONVERTER 23 37 GATE CONVERTER PULSE CLOCK A i (IMHzI x 38 MOVING 27STATIONARY MOVING TIME SERIES TIME SERIES TIME SERIES DELTIC DELTICDELTIC CoRRELAToR u CORRELATOR SI 33- W -39 4I- CONVERTER CONVERTER -43FILTER TO A SCAN DISPLAY 45 FILTER PEAK DET. PEAK DET.

AND SUMMER AND -I INTEGRATOR INTEGRATOR SAMPLING 6|) 59 PULSE RECTIFIERRECTIFIER (IKHZ) AND SUMMER AND I INTEGRATOR INTEGRATOR I Ir DELAYI-IARD R THRESHOLDING ..w HARD (IoopsEcI I..IMIT cIRCuIT LIMIT MANUAL lWi 5 Y o F s IIoo SEc) DELAY ,1 4 (SOHSEC) START 54 TIMER STOP BINARYRESET COUNTER BEARING ANGLE TO DISPLAY PULSE-ECHO PHASE DISCRIMINATORUSING DELTIC PROCESSING BACKGROUND OF THE INVENTION The invention hereindescribed was made in the course of or under a contract or subcontractthereunder, with the United States Navy.

This invention relates generally to signal processors for sonar andother acoustic pulse-echo systems, and more particularly to phasediscrimination processors capable of deriving from the phaserelationships of echo signals received at two spaced points ameasurement of the bearing angle to the location of the object fromwhich those signals were reflected, and capable also of accomplishingthis measurement with good reliability and accuracy even with signals ofvery low signal-to-noise ratio.

It is common practice in sonar, seismograph and other pulse-echo systemsto determine the bearing angle to a target or other reflective objectfrom which echo returns are received, by measuring the difference inphase of the reflected signals as received at two spaced points to thusarrive at a measure of the difference of travel time of reflections fromthe object. If the object lies squarely on boresight, i.e., if it lieson a line normal to the line joining the two points at which thereceivers are located, the transit times of signals to the two receiverswill be the same and the reflected signals will arrive at those pointswith zero phase difference between them. If the object is off boresight,however, there will be a difference in the distances between the objectand the two receivers and a corresponding difference in transit time tothem. The magnitude of this difference, which may be determined bymeasurement of the phase difference between the signals as received,provides a direct measure of the bearing angle of the object withrespect to boresight.

Particularly in the sonar applications, the characteristics of themedium in which the system must operate tend to make this phasedifference measurement a difficult one to accomplish with reliabilityand precision. Typically the received signals are buried deep in noiseor interference, and reverberation and the multiplicity of alternativepropagation modes or paths through the medium all tend to make verydifficult the extraction of useful signal from the receiver output.Where correlation or comparison of two such signals is required, as itis for phase discrimination purposes, this difficulty is doublycompounded.

Among the various known processor types which have been proposed forthis task is a particular form of cross correlator using timecompression to enable correlation in real time without loss of usefulsignals yet with manageable complexity of processor circuitry. The timecompression technique involved is commonly known by the term DELTIC,this being an acronym for Delay Line Time Compression. DELTIC processingis described in detail in many publications among which is US. Pat. No.2,958,039 to Anderson.

SUMMARY OF THE INVENTION The present invention has as its primaryobjective the provision of signal processors for sonar and otheracoustic pulse-echo systems, utilizing DELTIC processing for derivingbearing angle information in real time and with good reliability even inthe presence of reverberation and other noise. It is also an object ofthe invention to derive such bearing angle information using digitalsignal processing but with no significant loss of signal amplitudeinformation in the course of such processing, to thus enable improvedprecision of bearing angle measurement and indication.

The signal processor of this invention derives bearing angle informationby measurement of the phase difference of echo signals received at twospaced points, using in its processing operation also the transmittedsignal of which the echo signals are reflections. The two receivedsignals are each sampled at a common rate, A/D converted, and loadedinto one of two moving time series (MTS) DELTIC processors. Transmittedsignal polarity information is loaded into a stationary time series(STS) DELTIC, and the STS signal then correlated against each of the MTSsignals. The two correlation signals thus generated, after furtherprocessing, control the start and stop of timing means to providedirectly a measure of the phase difference of the received signals.Thresholding means are provided for establishing a threshold value whichmust be exceeded by one or more of the processed correlation signals, inwhich the received signal amplitude is preserved, in order to initiateeach phase difference measurement. If desired the two correlationsignals may also be combined with suitable processing for direct visualdisplay.

BRIEF DESCRIPTION OF THE DRAWING The foregoing and other objects,features and advantages of the invention will become more fully apparentand the invention further understood by reference to the followingdetailed description when read in conjunction with the accompanyingdrawings, wherein:

FIG. 1 is an electrical block diagram of phase discriminator apparatusin accordance with the invention shown embodied in sonar bearing anglemeasurement and display equipment;

FIG. 2 illustrates representative waveforms in the apparatus of FIG. I;and

FIG. 3 is a block diagram illustrating one implementation of certainelements of the apparatus of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT With continued reference to thedrawings, FIG. 1 illustrates a preferred embodiment of the pulse-echobearing angle measurement and display apparatus of the invention. Thisapparatus will be described in the following with particular referenceto its sonar application, but as previously indicated the invention hasapplication also to other pulse-echo systems such, for example, asseismic exploration equipments and ultrasound systems as used in medicaldiagnostics and the like.

Bearing angle measurement in the system as illustrated in FIG. 1 employsthree signal inputs, two being the target reflection or echo signals asreceived on leftand right-hand receptors 11 and 13, respectively, andthe third being the transmitted signal which is inputted as at 15. Eachof the receptors 11 and 13 may as indicated comprise a beamformerincluding an array of transducer elements together with associatedcircuitry for phasing the individual elements so as to form a beam andto steer the beam through a range of bearing angles. The two beamformersare conjointly controlled to steer their respective main lobes intosubstantial coincidence, so that reflections from a target or otherobject located at the particular bearing angle to which the beams thenare directed will produce outputs of approximately equal amplitude fromeach of the receptors 11 and 13.

Unless the target is squarely on boresight, however, return signals fromit will appear at the receptors 11 and 13 with a time difference, andconsequently a phase difference, between them. This difference in signalphase is proportional to the target bearing angle, and more particularlyis defined by the relation:

0 arc cos c(t, tz)/2a where c is the velocity of sound in thepropagation medium, a" is the effective spacing between the tworeceptors, and t, t, is the difference in arrival times of a signal asreceived by the receptors 11 and 13, respectively.

Since the receptor spacing a is known, and the velocity of sound withinthe medium adjacent the receptors is known or ascertainable, the task athand is the precise and real time measurement of the time difference r rAs previously noted the extraction of this time measure is often verydifficult in actual sonar operating environments by virtue of the verylow signalto-noise ratios typically obtainable in such environments andthe relatively poor correlation which sometimes exists between receivedsignal waveforms even with relatively closely spaced receptors.

To obtain the desired time difference measurement, the signals asreceived by each of the receptors 11 and 13 may be preprocessed throughsuch conventional signal-to-noise ratio enhancement steps aspreamplification, conversion and filtering, and automatic gain controlapplied as desired. The signals thus preprocessed are sampled insampling circuits 17 and 19 at a rate determined by a sampling pulseinput 21. The sampling pulse rate, shown in this representativeembodiment as being lKHz, is selected to be at least sufficiently highto avoid loss of useful information from the input signal.

The sampled signals are analog-to-digital converted in A/D converters 23and 25 which may be conventional in configuration. Conveniently theseA/D converters may be arranged to quantize the analog signal inputs toeight discrete levels utilizing a conventional three-bit digital code todefine the eight binary numbers required. Thus one of the three bitsrepresents the sign or polarity of each analog input sample and the twoother bits represent its amplitude, the three together defining thesample to the nearest of eight quantization levels.

After quantization the signals are time-compressed in moving time series(MTS) DELTIC processors 27 and 29, and subsequently correlated as at 31and 33 with a time compressed reference signal which is outputted by astationary time series (STS) DELTIC processor 35 common to both theleftand right-hand beam channels. This reference signal derives from thetransmitted pulse waveform input at 15. which is hard limited as at 36so as to retain only its polarity information in a digitalized formadapted to loading through transfer gate 37 into the STS DELTIC 35concurrently with the transmission of each pulse by the transmitter. Theoperation of the time compressors and other elements just described issynchronized by a clock input as at 38, which in the particularembodiment being described may be of the 1 MHz clock frequencyindicated. This clock conveniently may also be used to generate thesampling pulse input at 21, by 1000/1 frequency division in conventionalmanner.

The circuitry and function of the DELTIC processors will be furtherdescribed later in reference in FIG. 3; suffice it to say here that uponeach pulse transmission the STS DELTlC is loaded with an inputrepresenting the transmitted pulse waveform, or more accurately, withpolarity information descriptive of the clipped waveform. The transmitwaveform thus defined is DELTIC processed at 35 to provide atime-compressed replica of itself, which is outputted to the twocorrelators 31 and 33. The leftand right-hand receive beam signals aresampled, analog-to-digital converted to produce a sign bit and twoamplitude bits for each such signal sample, and the samples thentime-compressed in the MTS DELTIC procesosrs 27 and 29.

In the correlators 31 and 33, the sign bits in the timecompressedoutputs of the MTS DELTICS 27 and 29 are correlated against the outputof the STS DELTIC 35, which it will be recalled was loaded with polarityor sign information only. Each time polarity coincidence is foundbetween an STS sign bit and the sign bit of the leftor right-hand MTSsignal against which it is being correlated, the correlation signaloutput will reflect both the sign data and the corresponding amplitudedata, thus preserving the signal amplitude information through the timecompression and correlation processes as hereinafter more fullyexplained.

The leftand right-hand correlator output signals are reconverted toanalog form by D/A converters 39 and 41, and the products filtered as at43-45 to remove unwanted byproducts of the correlation and conversionprocesses. If the D/A converters do not themselves include means fordown-conversion of their outputs to the desired output frequency,down-converters of suitable type may be provided for this purposefollowing the filters 43 and 45.

After filtering, the correlation signals are hard limited as at 47-49,and the left-hand signal applied as one input to an AND element 51, tothus provide an enabling signal to AND element 51 upon the first axiscrossing of the correlation signal waveform following the peak value ofthe correlation function. Logic element 51 has as its other input amicrosecond gate pulse generated by a single-shot 52 which is triggeredto output this pulse to a flip-flop 54 by an input from the thresholdingcircuit 55 to be described. F lip-flop 54 has as enabling input thelKHzsampling pulse, delayed by 100 microseconds as indicated at 53. Thepurpose of this delay is to assure that the 100 microsecond gate asapplied to AND element 51 is delayed by a time period sufficient forcompletion of the. time compression and correlation operations whichwere intiated by that sampling pulse.

The thresholding circuit 55 has as its input the sum of the leftandright-hand correlation signals as fullwave rectified and integrated at57 and 59, and added in the summer 61. Since amplitude informationdescriptive of the leftand right-hand beam signals is preserved throughthe point of their application to the rectifier and integrator circuits57-59, the correlator outputs as summed and applied to the thresholdingcircuit enable precise control of the signal amplitude necessary toenable the gate 51 to start the timer operation to be described. Asindicated, thresholding circuit 55 is provided with a manuallyadjustable reference level, to enable adjustment of the threshold levelat which gate 51 may be triggered.

AND gate 51 applies its output to the START control of a timer 63 whichas indicated may be in the form of a binary counter of conventionaltype. Timer 63 is stopped by an input from the right-hand correlatorsignal after inversion at 64 and delay as at as through a fixed timeperiod of duration sufficient to allow a positive count to exist fortargets at least through the desired range of variation from boresight.The magnitude of this delay as, which in the particular embodimentillustrated may be 50 microseconds as indicated, may also be madevariable if desired to calibrate out any bearing offset produced byunequal phase shift through the leftand right-hand signal processingchannels.

The time count from timer 63 is as previously explained a direct measureof target bearing angle, and may be outputted directly to a display asindicated. Timer 63 then may be reset, as by a suitably timedelayedsampling pulse input through delay element 67, to prepare for the nextbearing angle measurement.

The operation of timer 63 may perhaps best be understood by reference toFIG. 2, the upper portion of which shows timing waveforms for aboresight target, and the lower portion for a target located to the leftof boresight. As shown, where the target is squarely on boresight theleftand right-hand beam signals, after delay of the right-hand signal at65, will be effectively 180 out of phase and the timer START and STOPsignals accordingly will be equally spaced along the time axis with aspacing equal to that of the delay element 65, 5O microseconds in theexample being described. If, however, the target is to the left of theboresight, then the waveforms will be shifted with respect to each otheras shown in the lower portion of FIG. 2, and the timer STOP signalgenerated by the right-hand input will be delayed with respect to thetimer START signal. The timer accordingly will indicate a time periodgreater than the nominal value of 50 microseconds, and the departurefrom this nominal value provides the desired measure of target bearingangle.

If desired, the leftand right-hand correlation signals may be used togenerate an additional display in the form of an A-scan presentationeither alone or time shared on a common display with the bearing angleinformation from timer 63. To accomplish this, the two correlationsignals are peak detected and integrated as at 71 and 73, andincoherently summed at 75. The output of summer 75, when displayed in anA-scan mode, is helpful to the operator in determining where to makebearing measurements particularly when signaltonoise ratios are low.

With reference now to FIG. 3, there is shown in greater detail onepossible implementation of certain of the processor elements of FIG. 1,specifically the transfer gate 19, the STS DELTlC 35, the MTS DELTlC 27for the left-hand beam, and the correlator 31 for that samd beam. Inpreference to the delay lines commonly used in DELTlC processors, thetime compression loops as illustrated each comprise a shift register ofconventional type. Use of these shift registers rather than delay linesimproves performance by eliminating delay line length adjustment anddrift in delay line length due to temperature changes.

The transfer gate 19 through which the STS DELTIC 35 is loaded comprisesa flip-flop 77 to which the input is the clipped transmit referencesignal, a Schmitt trigger 79 to which the input is a timing pulse fromthe transmitter modulator or driver of duration equal to that of thetransmitted pulse envelope, and a positive logic network including ANDgates 81, 82 and 83, and an OR gate 85. Gate 85 applies its outputs tothe STS shift register 87, which shiftS its contents one position to theright with each clock pulse input from the [MHZ clock designated hereand elsewhere in FIG. 3 by the letters CL." Data bits which have beenentered and subsequently shifted the full length of the register 87 aretransmitted via a flip-flop 89 to the correlator 31, and also aretransmitted as a feedback through logic element 82 for recirculation inthe DELTIC loop thus constituted.

in operation of the STS DELTIC just described, when the transmitter isenergized to output either a single pulse or a pulse train, Schmitttrigger 79 is activated and outputs a 1 to AND gate 82, the other inputsto which include a feedback from the flip-flop 89 and the lKl-llzsampling pulse signal as applied through a flipflop 91. The operation ofthe logic network 81-85 with the Schmitt trigger 79 thus activated is toload the shift register 87 with a time-compressed replica of the clippedtransmit waveform, such replica being assembled in the shift register byinputting an additional bit of data through flip-flop 77 once with eachof the 1 KHZ sampling pulses input to flip-flop 91, meanwhilerecirculating the bits previously stored in the register throughflip-flop 89, AND gate 83 and OR gate 85. Upon completion of thetransmission, Schmitt trigger 79 reverts to its normal state as shownand the operation of logic network 81-85 then becomes such as torecir'culate the stored replica indefinitely without change. It may benoted that this recirculation loop, which is completed through lead 91,includes only the shift register 87 and does not also include theflip-flop 89.

The MTS DELTIC comprises three time compression loops each including ashift register 93, one for the sign and one for each of the twoamplitude bits, designated S, 2' and 2 respectively in FIG. 3. The threeloops are identical, each comprising an input logic network which loadsa new bit of input information for each change in state of flip-flop 91at the lKHz sampling rate previously specified, and at other timesrecirculates the previously entered bits in the manner conventional toDELTIC processors.

It will be noted that these recirculation loops, unlike that of the STSDELTIC, include the flip-flop 95 which follows each shift register 93.The effect of this difference is to increase the recirculation time forthe MTS loops by 1 microsecond, i.e., one cycle of the lMi-lz clockpulse input, to thus provide for precession of the MTS with respect tothe STS in accordance with the usual practice in DELTIC correlationprocessing.

The outputs from the moving and stationary time series DELTICS aretransmitted to correlator 31 which comprises a logic network includingAND elements 97 and 98, EXCLUSIVE OR elements 99-101 and an OR element102 all connected as shown. Logic elements 97, 98 and 102 togetherconstitute a polarity coincidence detector the operation of which is tooutput a 1 whenever the output of the STS DELTIC and the sign bitoutputs of the MTS DELTIC are the same, i.e., both are ls or both are0's. In either case the OR element 102 will output a l to the logicelements 99, 100 and 101, and each of those elements will output itspresent MTS input, whether it be a 1 or a 0, directly. When polaritycoincidence is not found, OR element 102 will output a O and each of thelogic elements 99-101 then will output the inverse of its MTS input. Thedirect and inverse values of MTS data read out in this way through eachof the correlators 31 and 33 together define the correlation functionfor the respective leftor righthand beam, which function is then furtherprocessed as already explained in reference to FIG. 1.

Thus the DELTIC processor of the invention enables DELTlCtime-compression and correlation while preserving amplitude informationwith respect to the signals as correlated, and requires only relativelysimple and straightforward implementation to accomplish this purpose.The processor implementation may take any of several alternative forms,for example the DELTIC loops may utilize either delay line or shiftregisters as previously mentioned, and if preferred the thresholdingcircuit 55 could apply its output directly to the output of timer 63rather than through the AND element 51.

Many other modifications will occur to those skilled in the art and ittherefore should be understood that the appended claims are intended tocover all such modifications as fall within the true spirit and scope ofthe invention.

What is claimed as new and desired to be secured by Letters Patent ofthe United States is:

l. A pulse-echo signal processor for determining the phase difference oftwo received signals which include reflections of a transmitted signal.comprising:

a. means for sampling said two received signals at a common samplingrate and digitalizing each of the samples to provide first and seconddigital sample signals respectively describing one of said receivedsignals both as to polarity and amplitude;

be first and second moving time series (MTS) time compression means eachincluding a recirculation loop and means for loading into said loop atsaid sampling rate the polarity and amplitude information describing oneof said first and second digital sample signals, for recirculationtherein as a time compressed MTS signal;

c. stationary time series (STS) time compression means including arecirculation loop and means for digitalizing polarity information fromsaid transmitted signal and loading the polarity information at saidsampling rate as a time compressed STS signal in said loop forrecirculation therein, said STS time compression means having arecirculation time differing from that of said MTS means to therebyprovide precession of the MTS signals with respect to the STS signal;

d. first and second correlation means each operative to compare the STSsignal for polarity coincidence with one of said first and second MTSsignals and operative to output a correlation signal which preservesboth polarity and amplitude information describing each MTS signal forwhich polarity coincidence with the STS is found;

e. time measuring means responsive to the correlation signal outputtedby said first correlation means to initiate a time measurement andresponsive to the correlation signal outputted by said secondcorrelation means to conclude said measurement and indicate the phasedifference determination thus made; and

f. thresholding circuit means responsive to the amplitude of at leastone of said correlation signals to enable phase differencedeterminations only with respect to received signals for which said onecorrelation signal exceeds a threshold level.

2. A signal processor as defined in claim 1 further including means forrectifying, integrating and summing said correlation signals, andwherein said thresholding circuit means is responsive to the correlationsignals thus summed.

3. A signal processor as defined in claim 1 further including delaymeans interposed between said second correlation means and said timemeasuring means to thus provide a positive time measure irrespective ofthe direction of phase differences of said received signals.

4. A signal processor as defined in claim 1 further includingdigital-to-analog conversion and limiter means interposed between eachof said correlation means and said time measuring means.

5. A signal processor as defined in claim 1 further including means forpeak detecting, integrating and summing said correlation signals forvisual display.

1. A pulse-echo signal processor for determining the phase difference oftwo received signals which include reflections of a transmitted signal,comprising: a. means for sampling said two received signals at a commonsampling rate and digitalizing each of the samples to provide first andsecond digital saMple signals respectively describing one of saidreceived signals both as to polarity and amplitude; b. first and secondmoving time series (MTS) time compression means each including arecirculation loop and means for loading into said loop at said samplingrate the polarity and amplitude information describing one of said firstand second digital sample signals, for recirculation therein as a timecompressed MTS signal; c. stationary time series (STS) time compressionmeans including a recirculation loop and means for digitalizing polarityinformation from said transmitted signal and loading the polarityinformation at said sampling rate as a time compressed STS signal insaid loop for recirculation therein, said STS time compression meanshaving a recirculation time differing from that of said MTS means tothereby provide precession of the MTS signals with respect to the STSsignal; d. first and second correlation means each operative to comparethe STS signal for polarity coincidence with one of said first andsecond MTS signals and operative to output a correlation signal whichpreserves both polarity and amplitude information describing each MTSsignal for which polarity coincidence with the STS is found; e. timemeasuring means responsive to the correlation signal outputted by saidfirst correlation means to initiate a time measurement and responsive tothe correlation signal outputted by said second correlation means toconclude said measurement and indicate the phase differencedetermination thus made; and f. thresholding circuit means responsive tothe amplitude of at least one of said correlation signals to enablephase difference determinations only with respect to received signalsfor which said one correlation signal exceeds a threshold level.
 2. Asignal processor as defined in claim 1 further including means forrectifying, integrating and summing said correlation signals, andwherein said thresholding circuit means is responsive to the correlationsignals thus summed.
 3. A signal processor as defined in claim 1 furtherincluding delay means interposed between said second correlation meansand said time measuring means to thus provide a positive time measureirrespective of the direction of phase differences of said receivedsignals.
 4. A signal processor as defined in claim 1 further includingdigital-to-analog conversion and limiter means interposed between eachof said correlation means and said time measuring means.
 5. A signalprocessor as defined in claim 1 further including means for peakdetecting, integrating and summing said correlation signals for visualdisplay.